The SONET system provides a mechanism for mapping asynchronous DSx (DS1, DS3 etc.) type signals into the SONET payload envelope. There are no restrictions made on the traffic content or type and the mapping does not require that the DSx signals be network synchronous. To accomplish synchronization of SONET signals at an asynchronous node, pointers comprising a byte or word of information (normally eight bits) are used to define the start of the next SONET payload envelope such that it may move relative the SONET frame. Since the pointer comprises eight consecutive bits of the "data" bit stream (overhead and traffic data), prior art clock smoothing techniques produce a smoothed clock with excessive jitter that will detrimentally affect downstream communication circuits. In other words, the jitter is enough that economically practical prior art or older downstream phase locked loops cannot maintain synchronization.
The present invention accomplishes the incorporation of the large phase hits into the clock signal stream to be smoothed in a gradual manner by rerouting a portion of the clock signal representing the phase hit information to a high-pass filter and summing the output of the high-pass filter with the stream of clock pulses to be smoothed. Thus, the phase hit clock signal information is removed from the clock signal stream being smoothed over a relatively long period of time as compared to the duration of a single cycle of the clock signal. The combined signals are applied to a type two second order low-pass filter in the form of a phase locked loop to produce or maintain the smoothed clock output. The effect of this rerouting and summing high-pass filter output has a total system effect which is the same as low-pass filtering the phase hit process. In other words, the effect of the phase hit on the smoothed clock output signal is slowly introduced over a long period of time. While it may at first glance appear confusing, the present invention is diverting clock signal pulses involved in the phase hit process, high-pass filtering these diverted pulses, and summing the diverted pulses with the remaining data correlated pulses to effect the process of low-pass filtering a phase hit function.
The incoming discontinuous and smoothed output clocks are used in conjunction with an elastic buffer to write data into the buffer and read data out such that the data out is properly time coordinated with the smoothed clock.
While DSx format signals have been mentioned specifically herein and the SONET system is designed to integrate many different types of signals simultaneously and the present concept is not limited to DSx type signals or to SONET but can be utilized in any resynchronizing application where there are large phase hits occurring on some low frequency basis as compared to the frequency of the clock and which large phase hits need to be incorporated into a smoothed clock output.
It is thus an object of the present invention to provide an improved resynchronizing apparatus for a clock signal.